1. Field
The present disclosure pertains to the field of memories, memory controllers, devices having memory controllers, and memory systems.
2. Description of Related Art
Single transistor memories such as dynamic random access memories (DRAMs) are traditionally used because it is hard to beat the density that can be provided with a single cell memory. A capacitor stores a charge (or the lack thereof) to indicate memory state(s). However, a well known downside to this type of memory device is that the capacitive devices that store the state information lose their charge over time. As such, if the charge on the capacitive portion of the memory is not periodically refreshed, information may be lost.
A refresh cycle involves reading a portion of the dynamic memory, such as a row, and then writing the data back into the portion of memory. This is done periodically and frequently enough to avert any data loss due to decay of the charge in the capacitive structure. Since the data from the portion of the memory being refreshed must be read out, it is typically not possible, at least in a single ported memory, to access some portions of the dynamic memory during the refresh cycle. In other words, the refresh cycle typically blocks accesses to at least some regions of the memory device. Accordingly, intelligent memory controllers often control refresh cycles so that they can be scheduled so as to not interfere with more time-critical system memory accesses.
Current memory controllers generally use the same interface or portions of the same interface to send refresh commands or refresh row identifying information as are used to send memory access commands. Additionally, some memories provide a self-refresh function, whereby the memory itself refreshes dynamic cells. Typically, self-refresh is used to retain data during low power periods when the memory controller is disabled and/or does not access the memory device. However, self-refresh does not allow the memory controller to maintain control over which portions of the memory are being refreshed at a particular time.
Some memory devices also perform hidden refresh. A hidden refresh is a refresh performed by the memory device without being signaled by the memory controller to perform a refresh. Such hidden refreshes can impact timing because the memory device is not aware of the accesses that will be requested by the memory controller, making a conflict between the memory controller and the refresh possible. Thus, delays in satisfying memory requests due to refreshes may be encountered in some cases.